The first job to do is to fetch the instruction from the IAS. In order for a program to run it must have a start address. Below is a diagram of the main memory. The program will be stored within the IAS and the start address of that program will be loaded into the program counter register, PC. In this case the value in the PC will be 4320.

The value in PC is then copied to the memory address register and then incremented. The diagram below shows this transition.

What ever is pointed to in the MAR at this stage is then copied into the MDR register. As such the MAR register stores the address of the next instruction while the MDR will store the actual instruction itself. The instruction will be encoded at this stage so will just be a binary number. For our example we shall use the binary number

1000 1010 which has the denary value of 138.

Finally the contents of MDR are then copied over to the CIR, current instruction register. From here the instruction will be decoded in the next phase. As the instruction is being decoded, the next instruction can be fetched. The cycle is designed to perform as many actions of the CPU concurrently which improves the overall speed of the CPU. This is known as pipelining.